1. Field of Invention
The present invention relates to a clock and data recovery circuit. More particularly, the present invention relates to a clock and data recovery circuit for estimating jitter tolerance.
2. Description of Related Art
In modern times to take advantage of both topologies, some applications involve both parallel and serial communications. Therefore, demand for Serializer and De-serializer (SerDes) integrated circuits has increased. Clock and data recovery (CDR) circuit is one of the key building blocks for SerDes system. To tolerate the jitter existing in the system, the CDR circuit must have good jitter tolerance capability. In general, during the measurement/simulation of the jitter tolerance, various jitters with different amplitudes and frequencies are injected into a high speed input data stream, and then it is determined whether the recovered data has an error. However, the operation generally spends a lot of time and computation resources.